Phani Jayanth Jonnalagedda

Worked under Prof. Kamakoti Veezhinathan on 'Extending RISCV Vector ISA Support to the SHAKTI C-Class Microprocessor'. Engineering configurable Vector Functional Units to integrate in the processor pipeline.

Worked under Prof. Sparsh Mittal on 'Adding Matrix-Multiply Support to RISCV ISA'. Aimed to implement Matrix-Multiply Extensions and Approximate Instructions to accelerate AI-related Workloads. Benchmarked against RISCV Scalar and Vector-based implementations; simulating using Gem5 and Spike.

Worked on power optimization in the GPU submodules as a member of the GPU Design Team. Developed a Python-based framework to perform retention flop list analysis to identify potential redundant flops. Can be deployed over any design submodule and serves as a novel power curtailment technique.

Implemented Discrete Cosine Transform (DCT) in Hardware using Bluespec Verilog to accelerate H.264 Video Codec Module in the SHAKTI C-Class Processor. Reduced the computational latency by employing Butterfly architecture-based fast DCT algorithm. Fastened the implementation with a cosine look-up table and fixed-point operations, meeting the design requirements.

Studied the Hardware Security aspects of Deep Neural Networks, specifically Adversarial Robustness of Vision Transformers to attacks like FGSM, One-Pixel, and Bit-Flips. Performed Literature Review in 'Deep Learning for Underwater Image classification' published in 2022 IEEE Transactions on Neural Networks and Learning Systems.

Managed a 3-Tier Team of 50+ Electronics Enthusiasts and organized several club sessions and activites across campus. Project Head for the Mountable Heads-up Display for Helmets project that assists bikers in hassle-free navigation through traffic. Taught 40+ participants the concepts of Parallel Programming (OpenMP), CUDA, and RTOS at Shaastra (Annual Technical Fest of IITM) 2022.